Such a method and a data processing system suitable for this method are known from the I.E.E.E. Test Standard P 1149: "Standard Test Access Port and Boundary-Scan Architecture", (Draft), published by I.E.E.E. Standards Board, Institute of Electrical and Electronics Engineers, Inc.; 345 East 47.sup.th Street, New York, N.Y. 10017, U.S.A., more particularly section 6.9. The use of a shift register, in this case indicated as "scan register", is suggested therein as a standard test method: the "(boundary) scan test". In the most frequently occurring conditions, the test is effected in that via the parallel outputs of the scan register a test pattern is supplied to the circuit to be tested. Subsequently, the response to this test pattern is loaded into the register. Test patterns and responses are communicated with the environment whilst being serially shifted. The advantages of this method are:
a) a small number of external connections are required to make a system testable (four in the standard P 1149), PA1 b) the test method can be uniformly applied to different systems; PA1 c) with systems comprising different subsystems, test capabilities can be provided by a series arrangement of the registers of the subsystems; PA1 d) the requirements for test capabilities are so simple that they can be added to a system design with a small risk of errors, even automatically with a CAD program. PA1 a subsystem having input connections and at least one output connections which subsystem in an operating condition responds to elements from a first collection of input patterns at the input connections, which are included as admissible pairs of input patterns directly succeeding each other in a second collection of pairs, PA1 a serial shift register provided with a parallel output for supplying the input patterns to the input connection, PA1 a detector fed by information from the shift register for controlling, in response to previously determined information, the subsystem into a self-test condition and for then supplying a test characterization at the at least one output connection for further evaluation. According to one of its aspects, a self-test is controlled from the shift register via the parallel output and via at least part of the input connection while using a further control pattern at the input connection lying outside the defined collection.
For these reasons, the boundary scan test is a very suitable test method. In certain cases, however, the method of testing by use of test patterns is unsatisfactory, for example when for a good test a large number of different test patterns are required or when the circuit can have many different conditions, such as, for example, memories, so that a specially designed test program is necessary. In this case, the possibility is described of providing a built-in self-test device in subsystems (P 1149: BIST=Built-In Self-Test). Such a subsystem carries out a self-test program specially designed for the subsystem after a pattern interpreted as a start command has been received from the register. A characterization of the result is then made available via the scan register. Thus, an extensive test can be carded out rapidly, sometimes even in a number of parallel-connected subsystems.
However, in certain cases an insufficient number of (or absolutely no) connections are available to subsystems specially intended for the test. For example, the interface may be standardized, for example for IC types with connections defined for the type, in which event no special test connections are possible. This makes it impossible to include such subsystems in the normal manner in the scan circuit.